A phase locked loop (PLL) circuit is a circuit for generating an output signal locked with a phase of an input signal (a reference signal: REFCLK) input from outside. The PLL circuit has a function of removing a noise of a phase fluctuation component superimposed on the input signal, such as a so-called jitter or phase noise, and outputs the output signal from which a noise component is removed. A characteristic of the jitter noise removal has a low pass filter (LPF) characteristic, and a jitter noise having a frequency component greater than or equal to a cutoff frequency defined as a design parameter of the PLL is removed. In order to sufficiently remove a jitter noise, a setting of a lower cutoff frequency characteristic is desirable.
The PLL circuit is a type of automatic control loop circuit that causes a phase of the output signal to follow up the phase of the input signal, and the above-mentioned cutoff frequency corresponds to a loop band of automatic control. A speed of a response characteristic increases with an increase in the loop band in the automatic control. If the speed of the response characteristic is high, a time period taken to lock the phase of the output signal of the PLL with REFCLK serving as the input signal, in other words, a lock time is reduced.
In each of various kinds of systems utilizing the PLL, usually a time period taken to put a circuit into a steady state is desired to be shorter. Therefore, it is desirable that the above-mentioned lock time is as short a time period as possible. In this case, the cutoff frequency is set high. On the other hand, from a viewpoint of removal of the jitter noise superimposed on the input signal, it is desirable that the cutoff frequency is lower. In this way, in the PLL circuit, for a setting request for the cutoff frequency, a trade-off relationship between the characteristics of the noise removal and the response speed occurs. In order to fulfill conflicting requests, there is used a technology for switching between loop characteristics in such a manner that a high cutoff characteristic is selected to lock a phase with an input signal at the time of activating a circuit or the like and a low cutoff characteristic is selected at the time of being steady after the phase locking.
As the PLL circuit that switches between the loop characteristics, there is, for example, a technology for determining a convergence state of phase locking, based on a control voltage value of a voltage controlled oscillator (VCO) for generating a frequency of the output signal of the PLL circuit, and switching filter coefficients after the elapse of a given period of time (see, for example, Japanese Laid-open Patent Publication No. 7-142999). In addition, there is a technology for providing a phase comparator for loop filter switching determination, determining, based on an output of the phase comparator, a convergence state of phase locking, and switching filter coefficients (see, for example, Japanese Laid-open Patent Publication No. 4-100412).